TRANSPUTER ARCHITECTURE. What is Transputer ? Транспьютер (англ. transputer) элемент построения многопроцессорных систем, выполненный на одном кристалле. - презентация

1 TRANSPUTER ARCHITECTURE

2 What is Transputer ? Транспьютер (англ. transputer) элемент построения многопроцессорных систем, выполненный на одном кристалле большой интегральной схемы англ.процессорных интегральной схемы Transistor Computer. Goal was produce low cost low power chips to form a complete processor, just as transistors had earlier The first single chip computer designed for message-passing parallel systems, in 1980s, by the company INMOS (ныне подразделение STMicroelectronics). STMicroelectronics

3 Transputer Versions First generation 16 bit transputers: T212 T222 T bit transputers without a floating unit: T400 T414 T425 T bit transputers with a floating unit : T800 T801 T805 All have the same architecture, similar instruction sets and fully compatible communications links. Second Generation 64 bit transputer with a floating unit : T9000 Although general architecture much the same, it is a new design and is much more complex chip then its predecessors.

4 Транспьютер Т800 и коммутатор С004

5 TRANSPUTER ARCHITECTURE

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7 Memory All transputers address bytes 32 bit addresses gives 4 Gigabytes address space The range of addresses is unusual : starts at # and goes up to #7FFFFF, with # lying in the middle. Do not need to calculate unsigned arithmetic so it simplifies the ALU and reduce the number of instructions.

8 Transputer Memory Map

9 Processor The transputer processor is in some ways a conventional microprocessor. It executes one instruction at a time It has a small number of world-wide registers mostly dedicated to a particular purpose Areg, Breg and Creg: They are used to evaluate expressions and hold instruction operands and results. These are called as evaluation registers and arranged into a stack. Only the Areg is connected to internal buses, so only the Areg can be read or written to. Iptr, Oreg, Wreg: These are called sequential control registers: Instruction pointer (Iptr), holds the address of the next instruction. Operand register (Oreg), holds the operand for the current instruction. Workspace register (Wreg), holds the workspace pointer (Wptr) which is the address an area of memory called the local workspace.

10 Stack Organization Of Registers

11 Processor cont… Transputer supported two level priority levels, high- priority and low priority There is one chip microcode to support, automatically controls timesharing and queues between processes At any time a process may be either active or inactive. Transputer has such an architecture that inactive process do not use any processor time

12 Floating Point Unit A separate coprocessor, slave of the CPU, can run at the same time as the CPU but can not run a different parallel process There are 53 floating point instructions High level programming language to program is strongly advised rather than assembly It bases IEEE standards for the floating point format, operations and results

13 System Services In multi-processor systems it should be convenient to have a hierarchy of control. For example, a host should be able to boot up a network of transputers, detect when an error occurs and debug the network. These are achieved by means of reset, analyze, and error pins that called system service pins

14 Link Interface INMOS link is effectively a serial DMA port. It can be used for, interfacing with peripherals using a link adaptor, an ASIC (Application specific integrated circuit) chip can use a link to read and write directly into a transputer memory at high speed, most common to talk to another processor, usually anther transputer.

15 Link Interface cont.. The four links and processor have independent access to the memory The links designed so that transputers do not need to be synchronized in order to talk each other.However, need to agree nominal bit rate. So this means that transputers in a network may be driven either from a common clock or from separate clocks. Link Communication

16 Гибридная система

17 Link Protocols Transputers buffer only a single incoming data that every data packet is acknowledged First processor executes an input or output instruction and convey it to link. Then starts another parallel process When it is output it sends a data packed, and waits till an acknowledge arrives, then next package ….(chance to wait forever) When it is input, checks whether a data has come, if not waits, and sends an acknowledge as soon as get the package Synchronized but unbuffered Link Interface cont..

18 T 9000

19 Occam Parallel processing language written to be implemented in Transputer Exploits all the strength of transputer It uses the process and channel logic that a program designed for a transputer, could also be used in an array of transputers, with no change (Scalability feature) Designed to have a formal semantics suitable for automatic program transformations

20 Occam Basics Occam primitive is a process, five kinds: –Assignment x := y + 2 –Input keyboard ? char –Output screen ! Char –Skip SKIP -- NOP that terminates –Stop STOP –- NOP that never terminates Channels provide communication between processes –Unbuffered, point-to-point synchronous communication –Channels have declared protocol types c ? yc ! x Channel c

21 Composing Sequential Processes SEQ executes sub-processes sequentially SEQ keyboard ? char –- read char from keyboard screen ! char -- write char to screen Can do replicated SEQ SEQ i = 0 FOR array.size stream ! data.array[i] -- equivalent to SEQ stream ! data.array[0] stream ! data.array[1]...

22 Composing Parallel Processes PAR executes sub-processes in parallel PAR keyboard(kbd.to.ed) editor(kbd.to.ed,ed.to.screen) screen(ed.to.screen) screen editor keyboard