Verilog Tutorial Ando KI Spring 2009. Copyright © 2007-2009 by Ando KiVerilog tutorial ( 2 ) Contents Design flow overview Hello world GUI based Command. - презентация

1 Verilog Tutorial Ando KI Spring 2009

2 Copyright © by Ando KiVerilog tutorial ( 2 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example Example design Simulation Synthesis Gate-level simulation Appendix: Run adder with GUI

3 Copyright © by Ando KiVerilog tutorial ( 3 ) Standard FPGA-based design flow

4 Copyright © by Ando KiVerilog tutorial ( 4 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example Example design Simulation Synthesis Gate-level simulation

5 Copyright © by Ando KiVerilog tutorial ( 5 ) Hello world Try a simple example to display text on the screen. GUI based Step 1: coding using text editor, e.g., vi or vim. Step 2: compilation Step 3: simulation Command based Step 1: coding using text editor, e.g., vi or vim. Step 2: compilation Step 3: simulation

6 Copyright © by Ando KiVerilog tutorial ( 6 ) Hello world: coding Make a directory say ex_hello Go to the directory Create a Verilog file hello.v module top; initial $display(Hello world!); endmodule Initial construct is executed at the start of simulation. initial_construct ::= initial statement Display task puts information on the terminal. display_task ::= $display ( list_of_arguments ); Top-level module contains whole design, which does not have port. module and endmodule specifies a block. DIY

7 Copyright © by Ando KiVerilog tutorial ( 7 ) Create a new project Invoke ModelSim File New Project Specify Project Name and Project Location DIY

8 Copyright © by Ando KiVerilog tutorial ( 8 ) Add existing file Add the Verilog design file DIY

9 Copyright © by Ando KiVerilog tutorial ( 9 ) Compile DIY

10 Copyright © by Ando KiVerilog tutorial ( 10 ) Compile DIY

11 Copyright © by Ando KiVerilog tutorial ( 11 ) Compile DIY

12 Copyright © by Ando KiVerilog tutorial ( 12 ) Simulation DIY

13 Copyright © by Ando KiVerilog tutorial ( 13 ) Quit There should be hello.mpf, which is ModelSim project file. DIY

14 Copyright © by Ando KiVerilog tutorial ( 14 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example Example design Simulation Synthesis Gate-level simulation

15 Copyright © by Ando KiVerilog tutorial ( 15 ) Command based simulation vlib specifies where compiled library locates. vlog compiles Verilog code. vsim simulate the design with a given command. You can use any script language such as MS-DOS, shell and so on. vlib work vlog hello.v vsim -c -do "run -all; quit" work.top The vlib command creates a design library. vlib [options] The vlog command compiles Verilog source code into a specified working library (or to the work library by default). vlog [options] The vsim command is used to invoke the VSIM simulator. vsim [-c] [-do ].

16 Copyright © by Ando KiVerilog tutorial ( 16 ) Command based simulation result DIY

17 Copyright © by Ando KiVerilog tutorial ( 17 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example Example design Simulation Synthesis Gate-level simulation

18 Copyright © by Ando KiVerilog tutorial ( 18 ) Module declaration Module is the basic design unit. Module must be declared. prepare Module can be instantiated. use A module definition shall be enclosed between the keywords module and endmodule. Module syntax module module_name ( list of ports ); // in, out, inout port declarations // signal/wire/reg declarations // data variable declarations // sub-module instantiation and connection // functional blocks: initial, always, function, task endmodule module ModF (A, B, C); input A; inout [7:0] B; output [7:0] C; // declarations // description of f endmodule ModF f f A B C

19 Copyright © by Ando KiVerilog tutorial ( 19 ) Module instantiation module ModG (AA, BB, CC); input AA; inout [7:0] BB; output [7:0] CC; wire a; wire [7:0] b; // description of g ModG Umodg (.A(a),.B(b),.C(CC)); endmodule ModG g g AA BB CC f f a b ModF f f A B C instantiation Port connection Instance name Module name

20 Copyright © by Ando KiVerilog tutorial ( 20 ) Connection through port Port connection rules Input port must be net (i.e. wire). Output port can be either net or reg. Inout port must be net. input output inout reg or net net reg or net

21 Copyright © by Ando KiVerilog tutorial ( 21 ) Test-bench A test-bench is a layer of code that is created to apply input patterns (stimulus) to the DUT (design under test) and to determine whether the DUT produces the outputs expected. A test-vector is a set of values for all the expected input ports (stimuli) and expected values for the output ports of a module under test. A test-bench that is created to apply inputs, sample the outputs of the DUT, and compare the outputs with the expected (golden) results is called a self- checking test-bench.

22 Copyright © by Ando KiVerilog tutorial ( 22 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example What is adder Directory structure Example design Simulation Synthesis Gate-level simulation

23 Copyright © by Ando KiVerilog tutorial ( 23 ) What is adder An adder is a digital circuit that performs addition of numbers. The half adder adds two one-bit binary numbers (A and B). The output is the sum of the two bits (S) and the carry (C). The full-adder circuit adds three one-bit binary numbers (C, A and B) and outputs two one-bit binary numbers, a sum (S) and a carry (C). Multi-bit adder Ripple carry adder Carry look-ahead adders Picture has been adopted from Wikipedia (

24 Copyright © by Ando KiVerilog tutorial ( 24 ) Directory structure adder design sim syn Verilog source code folder HDL simulation folder Synthesis folder Directory structure sim.gate Gate-level simulation folder incite5000 iNSPIRE folder for specific FPGA board sim.fpga FPGA-based simulation folder (emulation)

25 Copyright © by Ando KiVerilog tutorial ( 25 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example What is adder Directory structure Example design Simulation Synthesis Gate-level simulation

26 Copyright © by Ando KiVerilog tutorial ( 26 ) Example design See the design directory top.v full_adder.v half_adder_gate.v half_adder_rtl.v stimulus.v full_adder_ref.v checker.v

27 Copyright © by Ando KiVerilog tutorial ( 27 ) Full adder (1/3) module full_adder(sum,cout,in1,in2,cin,clk,resetb); output sum, cout; input in1, in2, cin; input clk, resetb; wire sum, cout; reg rin1, rin2, rcin; wire s1, c1, s2, c2; (posedge clk or negedge resetb) begin if (resetb==1'b0) begin rin1 <= 1'b0; rin2 <= 1'b0; rcin <= 1'b0; end else begin rin1 <= in1; rin2 <= in2; rcin <= cin; end half_adder_gate ha1 (.S(s1),.C(c1),.A(rin1),.B(rin2)); half_adder_rtl ha2 (.S(s2),.C(c2),.A(s1),.B(rcin)); assign sum = s2; assign cout = c1|c2; endmodule

28 Copyright © by Ando KiVerilog tutorial ( 28 ) Full adder (2/3) module full_adder(sum,cout,in1,in2,cin,clk,resetb); output sum, cout; input in1, in2, cin; input clk, resetb; wire sum, cout; reg rin1, rin2, rcin; wire s1, c1; wire s2, c2; (posedge clk or negedge resetb) begin if (resetb==1'b0) begin rin1 <= 1'b0; rin2 <= 1'b0; rcin <= 1'b0; end else begin rin1 <= in1; rin2 <= in2; rcin <= cin; end half_adder_gate ha1 (.S(s1),.C(c1),.A(rin1),.B(rin2)); half_adder_rtl ha2 (.S(s2),.C(c2),.A(s1),.B(rcin)); assign sum = s2; assign cout = c1|c2; endmodule module name ports port directions internal signals sub module instantiation internal design description

29 Copyright © by Ando KiVerilog tutorial ( 29 ) Full adder (3/3) module full_adder(sum,cout,in1,in2,cin,clk,resetb); output sum, cout; input in1, in2, cin; input clk, resetb; wire sum, cout; reg rin1, rin2, rcin; wire s1, c1; wire s2, c2; (posedge clk or negedge resetb) begin if (resetb==1'b0) begin rin1 <= 1'b0; rin2 <= 1'b0; rcin <= 1'b0; end else begin rin1 <= in1; rin2 <= in2; rcin <= cin; end half_adder_gate ha1 (.S(s1),.C(c1),.A(rin1),.B(rin2)); half_adder_rtl ha2 (.S(s2),.C(c2),.A(s1),.B(rcin)); assign sum = s2; assign cout = c1|c2; endmodule Verilog data types: net and variable net: wire variable: reg, integer, real... Sub-module instantiation with named port connection; refer to positional pot connection. Continuous assignment places values to nets whenever the value of the right-hand side changes. This always block runs when the following condition occurs. positive edge of clk negative edge of resetb Procedural assignment places values to variables within always, initial and so on. ==: equality check operator <=: non-blocking assignment operator |: bit-wize OR operator

30 Copyright © by Ando KiVerilog tutorial ( 30 ) Half adder structural model (gate level) module half_adder_gate (S, C, A, B); output S, C; input A, B; and UAND (C, A, B); xor UXOR (S, A, B); endmodule A B S C Structural model: instantiation of primitives and modules.

31 Copyright © by Ando KiVerilog tutorial ( 31 ) Half adder data-flow model (RTL) module half_adder_rtl (S, C, A, B); output S, C; input A, B; wire S, C; assign C = A & B; assign S = A ^ B; endmodule A B S C Data-flow model: continuous assignments.

32 Copyright © by Ando KiVerilog tutorial ( 32 ) Test-bench: stimulus module stimulus(out1,out2,out3,clk,resetb); output out1,out2,out3; input clk,resetb; reg out1,out2,out3; initial begin out1 <=0; out2 <=0; out3 <=0; wait (resetb==1'b0); wait (posedge clk); out1=1; out2=0; (posedge clk); out1=0; out2=1; (posedge clk); out1=1; out2=1; (posedge clk); out1=0; out2=0; (posedge clk); out1=1; out2=0; (posedge clk); out1=0; out2=1; (posedge clk); out1=1; out2=1; (posedge clk); repeat (posedge clk); $finish; end endmodule <=: non-blocking assignment operator Initial construct is executed at the start of simulation. =: blocking assignment operator repeat: Executes a statement a fixed number of times. wait: It blocks until the condition becomes waits until the specified event occurs. The finish system task simply makes the simulator exit and pass control back to the host computer operating system.

33 Copyright © by Ando KiVerilog tutorial ( 33 ) Test-bench: checker module checker(in1,in2,cin,sum,cout,sumr,coutr,clk,resetb); input in1,in2,cin,sum,cout,sumr,coutr,clk,resetb; (clk) begin if ({cout,sum}=={coutr,sumr}) $display($time,,"correct"); else $display($time,,"error result=%b expect=%b", {cout, sum}, {coutr,sumr}); end endmodule Time system function returns an integer that is a 64-bit time, scaled to the timescale unit of the module that invoked it. time_function ::= $time ; Display task puts information on the terminal. display_task ::= $display ( list_of_arguments );

34 Copyright © by Ando KiVerilog tutorial ( 34 ) Test-bench: full_adder_ref module full_adder_ref(sum,cout,in1,in2,cin,clk,resetb); output sum, cout; input in1, in2, cin; input clk, resetb; wire sum, cout; reg rin1, rin2, rcin; wire s1, c1; wire s2, c2; (posedge clk or negedge resetb) begin if (resetb==1'b0) begin rin1 <= 1'b0; rin2 <= 1'b0; rcin <= 1'b0; end else begin rin1 <= in1; rin2 <= in2; rcin <= cin; end assign {cout, sum} = rin1+rin2+rcin; endmodule assign: Continuous assignment places values to nets whenever the value of the right-hand side changes. Concatenation operator ({, }) combines two or more in order to form wider bits.

35 Copyright © by Ando KiVerilog tutorial ( 35 ) Test-bench: top module top; wire sum, cout, in1, in2, cin; reg clk; full_adder fa (.sum(sum),.cout(cout),.in1(in1),.in2(in2),.cin(cin)); stimulus st (.out1(in1),.out2(in2),.out3(cin),.clk(clk)); checker ck (.in1(in1),.in2(in2),.cin(cin),.sum(sum),.cout(cout),.clk(clk)); initial begin clk = 0; forever #5 clk = ~clk; end initial begin $dumpfile("wave.vcd"); $dumpvars(1) end endmodule Dumpfile task specify the name of the VCD file. dumpfile_task ::= $dumpfile( filename ) ; Dumpvars task puts information on the terminal. dumpvars_task ::= $dumpvars ( level, [ list_of_mod_or_var ); Initial construct is executed at the start of simulation. initial_construct ::= initial statement Forever statement continuously executes a statemet. forever_statement ::= forever statement Top-level module contains whole design, which does not have port.

36 Copyright © by Ando KiVerilog tutorial ( 36 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example What is adder Directory structure Example design Simulation Synthesis Gate-level simulation

37 Copyright © by Ando KiVerilog tutorial ( 37 ) Command based simulation See sim directory vlib work vlog../design/top.v vlog../design/full_adder.v vlog../design/half_adder_gate.v vlog../design/half_adder_rtl.v vlog../design/stimulus.v vlog../design/full_adder_ref.v vlog../design/checker.v vsim -c -do "run -all; quit" work.top DIY

38 Copyright © by Ando KiVerilog tutorial ( 38 ) Simulation result with VCD Run GTKwave to see wave form DIY

39 Copyright © by Ando KiVerilog tutorial ( 39 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example What is adder Directory structure Example design Simulation Synthesis Gate-level simulation

40 Copyright © by Ando KiVerilog tutorial ( 40 ) Synthesis with command-line See the syn directory set top=full_adder xst -ifn xst_option.xst -ofn %top%.log ngc2edif -bd angle -w %top%.ngc %top%.edif netgen –w –ofmt verilog %top%.ngc %top%_gate.v Windows batch command file RunMe.bat set -tmpdir. run -ifmt MIXED -top $top -p $device -ifn $design -vlgincdir $inc_dir -ofn $top -ofmt NGC …… -iobuf NO -fsm_encoding User …… -iob auto xst_option.xst verilog xst../design/full_adder..v verilog xst../design/half_adder_gate.v verilog xst../design/half_adder_rtl.v xst_list.xst Important notice: iNCITE does not need IO pads. FSM encoding can be changed without this option Generate gate-level design DIY

41 Copyright © by Ando KiVerilog tutorial ( 41 ) Contents Design flow overview Hello world GUI based Command based Module Declaration Instantiation Port Test-bench Adder example What is adder Directory structure Example design Simulation Synthesis Gate-level simulation

42 Copyright © by Ando KiVerilog tutorial ( 42 ) Command based gate-level simulation See sim.gate directory vlib work vlog../design/top.v vlog../design/stimulus.v vlog../design/checker.v vlog../syn/full_adder_gate.v^ +libext+.v^ -y %XILINX%/verilog/src/simprims^ -y %XILINX%/verilog/src/unisims vsim -c -do "run -all; quit" work.top work.glbl Generated gate-level design while logic synthesis Gate-level library for Xilinx DIY

43 Copyright © by Ando KiVerilog tutorial ( 43 ) Invoking ModelSim from start menu

44 Copyright © by Ando KiVerilog tutorial ( 44 ) File->New->Project

45 Copyright © by Ando KiVerilog tutorial ( 45 ) Specify project name and location

46 Copyright © by Ando KiVerilog tutorial ( 46 ) File->Add to Project->Existing File

47 Copyright © by Ando KiVerilog tutorial ( 47 ) Add files

48 Copyright © by Ando KiVerilog tutorial ( 48 ) After adding files

49 Copyright © by Ando KiVerilog tutorial ( 49 ) Compile->Compile All

50 Copyright © by Ando KiVerilog tutorial ( 50 ) After compilation

51 Copyright © by Ando KiVerilog tutorial ( 51 ) View->Debug Windows->Wave

52 Copyright © by Ando KiVerilog tutorial ( 52 ) After adding wave window

53 Copyright © by Ando KiVerilog tutorial ( 53 ) Select Library tab

54 Copyright © by Ando KiVerilog tutorial ( 54 ) Run simulation with top-level

55 Copyright © by Ando KiVerilog tutorial ( 55 ) After simulation

56 Copyright © by Ando KiVerilog tutorial ( 56 ) Selecting signals to be view

57 Copyright © by Ando KiVerilog tutorial ( 57 ) After selection

58 Copyright © by Ando KiVerilog tutorial ( 58 ) Run-All

59 Copyright © by Ando KiVerilog tutorial ( 59 ) Home work AccumulatorMAC (multiply-accumulate) a a + b * c