® Multi-Port SRAM Overview

® Slide 2 Objectives n What are Multi-Port SRAMs? n Why are they needed? n Arbitration Features l Busy l Interrupt l Semaphore n Types: l Dual-Port l FourPort l Bank Switchable l SARAMs Address Data Control Static Random Access Memory Left PortRight Port

® Slide 3 SRAM vs. Multi-Port SRAM ADDRESS DATA Control Static Random Access Memory Address Data Control Static Random Access Memory Left PortRight Port

® Slide 4 Direct Memory Access

® Slide 5 Multi-Port Memory Access

® Slide 6 Simultaneous Access Read / Write Read Write ReadWrite Read or

® Slide 7 Busy Flag Memory Locations Busy Logic Control leftControl right Address right Address left Data rightData left Busy leftBusy right n Compare Addresses n If addresses are the same: l Busy based on who was first l If simultaneou s, busy logic will pick

® Slide 8 Interrupts Right Interrupt Memory location Left Interrupt Memory location Write sets Right Int.Read clears Right Int. Read clears Left Int.Write sets Left Int. n Interrupts controlled using two highest memory locations n Contents tells interrupted device what to do

® Slide 9 Semaphores n One Semaphore contains two latches, one for each port. n Initially Clear n Left side requests then right side requests n Left side reads request granted, right side reads request denied n Left side clears, right side request may now be accepted CLEAR LeftRight SET CLEAR SET CLEAR Semaphore

® Slide 10 FourPort SRAM PORT 1 PORT 2 Static Random Access Memory Address Data Control Address Data Control PORT 3 PORT 4

® Slide 11 Bank-Switchable Dual-Port SRAM 8K x 16 Bank 1 8K x 16 Bank 0 8K x 16 Bank 2 8K x 16 Bank 3 Address RAddress L Bank Addr LBank Addr R Data LData R Control LControl R Bank Select n Uses Standard SRAM n Bank accessible by only one port at a time n Bank select assigns banks to ports

® Slide 12 Sequential Access RAM (SARAM) Address Data Control Static Random Access Memory Random Access Port Sequential Access Port Clock n One port accesses memory locations randomly n Second port accesses memory locations sequentially.

® Slide 13 Summary n Multiple device high speed memory access n No DMA required n Arbitration may be required n Types: l Dual Port l FourPort l Bank Switchable l Sequential Access RAM Address Data Control Static Random Access Memory Left PortRight Port