Lecture 11 Computer Architecture CPU Structure and Function

CPU Function CPU must: –Fetch instructions –Interpret/decode instructions –Fetch data –Process data –Write data

CPU With Systems Bus

Registers CPU must have some working space (temporary storage) - registers Number and function vary between processor designs - one of the major design decisions Top level of memory hierarchy

User Visible Registers General Purpose Data Address Condition Codes

General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data: accumulator (AC) Addressing: segment (cf. virtual memory), stack (points to top of stack, cf. implicit addressing)

General Purpose Registers (2) Make them general purpose –Increased flexibility and programmer options –Increased instruction size & complexity, addressing Make them specialized –Smaller (faster) but more instructions –Less flexibility, addresses implicit in opcode

How Many GP Registers? Between Less = more memory references More takes up processor real estate See also RISC

How big? Large enough to hold full address Large enough to hold full data types But often possible to combine two data registers or two address registers by using more complex addressing (e.g., page and offset)

Condition Code Registers – Flags Sets of individual bits, flags –e.g., result of last operation was zero Can be read by programs –e.g., Jump if zero – simplifies branch taking Can not (usually) be set by programs

Control & Status Registers Program Counter (PC) Instruction Register (IR) Memory Address Register (MAR) – connects to address bus Memory Buffer Register (MBR) – connects to data bus, feeds other registers

Program Status Word A set of bits Condition Codes: –Sign (of last result) –Zero (last result) –Carry (multiword arithmetic) –Equal (two latest results) –Overflow Interrupts enabled/disabled Supervisor/user mode

Supervisor Mode Intel ring zero Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs

MC68000 and Intel registers Motorola: –Largely general purpose registers – explicit addressing –Data registers also for indexing –A7 and A7 for user and kernel stacks Intel –Largely specific purpose registers – implicit addressing –Segment, Pointer & Index, Data/General purpose –Pentium II – backward compatibility

Indirect Cycle Same address can refer to different arguments (by changing the content of the location the address is pointing to) Indirect addressing requires more memory accesses to fetch operands Can be thought of as additional instruction subcycle

Instruction Cycle with Indirect

Instruction Cycle State Diagram

Data Flow (Instruction Fetch) PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1

Data Flow (Fetch Diagram)

Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed –Rightmost n bits of MBR (address part of instruction) transferred to MAR –Control unit requests memory read –Result (address of operand) moved to MBR

Data Flow (Indirect Diagram)

Data Flow (Execute) May take many forms, depends on instruction being executed May include –Memory read/write –Input/Output –Register transfers –ALU operations

Data Flow (Interrupt) Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g., stack pointer) loaded to MAR MBR written to memory according to content of MAR PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched

Data Flow (Interrupt Diagram)

Prefetch Fetch involves accessing main memory Execution of ALU operations do not access main memory Can fetch next instruction during execution of current instruction, cf. assembly line Called instruction prefetch

Improved Performance But not doubled: –Fetch usually shorter than execution (cf. reading and storing operands) Prefetch more than one instruction? –Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance

Two Stage Instruction Pipeline

Pipelining (six stages) 1.Fetch instruction 2.Decode instruction 3.Calculate operands (i.e., EAs) 4.Fetch operands 5.Execute instructions 6.Write result Overlap these operations

Timing Diagram for Instruction Pipeline Operation (assuming independence)

The Effect of a Conditional Branch/Interrupt on Instruction Pipeline Operation

Six Stage Instruction Pipeline

Speedup Factors with Instruction Pipelining: nk/(n+k-1) (ideally)

Pipeline Hazards Resource hazards Data hazards Control hazards

Resource hazards

Data hazards ADD EAX, EBX /* EAX = EAX + EBX SUB ECX, EAX /* ECX = ECX – EAX

Data hazards Read after write (RAW) Write after read (RAW) Write after write (RAW)

Control hazards. Dealing with Branches A variety of approaches have been taken for dealing with conditional branches: 1.Prefetch Branch Target 2.Loop buffer 3.Branch prediction 4.Delayed branching (see RISC)