Modeling Sequential Logic Ando KI June 2009. Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Sequential Components D Flip-Flop Counter Shift.

Презентация:



Advertisements
Похожие презентации
Modeling Combinational Logic Ando KI June Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Combinational Components Multiplexer Encoder.
Advertisements

Verilog RTL Coding Guideline for Synthesis and Simulation Ando KI June 2009.
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters.
Parity Generator & Checker Ando KI June Copyright © 2009 by Ando KiModule overview ( 2 ) Objectives Learn what is parity. Learn how to use Verilog.
Verilog - Behavioral Modeling - Ando KI Spring 2009.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Part 2 – Sequential.
Verilog RTL Coding Guideline Ando KI June Copyright © by Ando KiLecture overview ( 2 ) Contents Purposes of coding guidelines Principles.
Verilog - Hierarchy, Module, Port and Parameter - Ando KI Spring 2009.
Convolutional Codes Mohammad Hanaysheh Mahdi Barhoush.
Verilog Tutorial Ando KI Spring Copyright © by Ando KiVerilog tutorial ( 2 ) Contents Design flow overview Hello world GUI based Command.
Lecture # Computer Architecture Computer Architecture = ISA + MO ISA stands for instruction set architecture is a logical view of computer system.
By Intersil Corporation. The ICL8038 waveform generator is a monolithic integrated circuit capable of producing high accuracy sine, square, triangular,
Verilog - Gate and Switch Level Modeling - Ando KI Spring 2009.
© 2005 Cisco Systems, Inc. All rights reserved.INTRO v Operating and Configuring Cisco IOS Devices Configuring a Router.
© 2009 Avaya Inc. All rights reserved.1 Chapter Four, UMS Web Services Module One – UMS.
© 2005 Cisco Systems, Inc. All rights reserved.INTRO v Ensuring the Reliability of Data Delivery Establishing a TCP Connection.
Sequences Sequences are patterns. Each pattern or number in a sequence is called a term. The number at the start is called the first term. The term-to-term.
Module III Taub Ch.6 PSK QPSK M-ary PSK FSK M-ary FSK MSK.
© 2006 Avaya Inc. All rights reserved. Network Small Community Network Network Small Community Network.
© 2005 Cisco Systems, Inc. All rights reserved.INTRO v Module Summary LANs are networks that are located in a limited area, with their components.
Транксрипт:

Modeling Sequential Logic Ando KI June 2009

Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Sequential Components D Flip-Flop Counter Shift Register

Copyright © 2009 by Ando KiModule overview ( 3 ) D Flip-Flop Description The D flip-flop is an edge-triggered memory device (cell primitive) that transfers a signals value on its D input, to its Q output, when an active edge transition occurs on its clock input. The output value is held until the next active clock edge. DCKQQ X0Q_ X1 D CK Q Truth tableCircuit symbol Q

Copyright © 2009 by Ando KiModule overview ( 4 ) D Flip-Flop module dff ( CK, D, Q ); inputCK; inputD; outputQ; regQ; CK) Q <= D; endmodule Verilog coding Modeling a D Flip-Flop

Copyright © 2009 by Ando KiModule overview ( 5 ) D Flip-Flop Simulation Go to../project_sequential/dff Run RunMe.bat Note that MODEL_TECH environment variable should be defined, which reflects where ModelSim is installed. SET MODEL_TECH=C:\Modeltech_xe_starter SET MODEL_TECH=C:\Modeltech_se

Copyright © 2009 by Ando KiModule overview ( 6 ) D Flip-Flop Waveform

Copyright © 2009 by Ando KiModule overview ( 7 ) Counter Description A register that goes through a predetermined sequence of binary values, upon the application of input pulses on one ore more inputs, is called a counter. Counters count the number of occurrences of an event.

Copyright © 2009 by Ando KiModule overview ( 8 ) Counter module counter ( clk, reset, count, enable ); input clk; input reset; input enable; output [7:0] count; reg [7:0] count; clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end endmodule Verilog coding Modeling a 8bit counter

Copyright © 2009 by Ando KiModule overview ( 9 ) Counter Simulation Go to../project_sequential/counter Run RunMe.bat

Copyright © 2009 by Ando KiModule overview ( 10 ) Counter Waveform

Copyright © 2009 by Ando KiModule overview ( 11 ) Shift Register Description Shift register is a group of flip flops set up in a linear fashion which have their inputs and outputs connected together in such a way that the data are shifted down the line when the circuit is activated. Shift register

Copyright © 2009 by Ando KiModule overview ( 12 ) Shift Register module shift_register (clk, shift, sr_in, sr_out); input clk, shift; input sr_in; output sr_out; reg [7:0] sr; clk) begin if (shift == 1'b1) begin sr[7:1] <= sr[6:0]; sr[0] <= sr_in; end assign sr_out = sr[7]; endmodule Verilog coding Modeling an 8-bit shift-left register with a positive-edge clock, serial in, and serial out

Copyright © 2009 by Ando KiModule overview ( 13 ) Shift Register Simulation Go to../project_sequential/shift_register Run RunMe.bat

Copyright © 2009 by Ando KiModule overview ( 14 ) Shift Register Waveform