Verilog - Hierarchy, Module, Port and Parameter - Ando KI Spring 2009

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 2 ) Contents Verilog HDL world Hierarchical structure Hierarchical structure example Module declaration Module instantiation Port and connection Port connection rules Hierarchical names Scope rule Parameter

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 3 ) Verilog-HDL world A system consists of a set of components, which forms a hierarchical structure. The component is an instantiation of design entity. The design entity is a design unit, which is module. A design unit can instantiate other design units, but a design unit cannot declare other design unit. A module can be instantiated as many as needed. System Module Process Module Process

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 4 ) Hierarchical structure (1/2) Hierarchical hardware structure Module can embed other modules by creating instances of its lower modules. Modules are connected through ports (input, output, inout). Modules communicate each other through ports. Each module definition stands alone. The definition cannot be nested. Module definition does not nest. One module definition shall not contain the text of another module definition. A module definition nests another module by instantiating. Module can instantiate another module (lower-level module) into itself in order to incorporate a copy of the lower-level module. Instantiation allows one module to incorporate a copy of another module into itself. Top-level module is included in the source text, but is not instantiated.

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 5 ) Module 0 Module 1 Hierarchical structure (2/2) Module 0 Module 1 Module 2 Module 4 Module 3 Module 5 Module 0 Module 1 Module 2 Module 3 Module 4 Module 3 Module 5 Module 3 Module 5 Module 4 Module 2 Module 3 Module 5 Instantiation and connection Hierarchy relationship Top-level module Module definitions

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 6 ) Hierarchical structure example 8-bit SDRAM module 4-byte SDRAM DIMM module 8-bit SDRAM module CPU North bridge South bridge Graphic controller DIMM PCI bus Module declare Multiple instantiation within a module Module declare A computer system declare DIMM

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 7 ) Module declaration Module is the basic design unit. Module must be declared. prepare Module can be instantiated. use A module definition shall be enclosed between the keywords module and endmodule. Module syntax module module_name ( list of ports ); // in, out, inout port declarations // signal/wire/reg declarations // data variable declarations // sub-module instantiation and connection // functional blocks: initial, always, function, task endmodule module ModF (A, B, C); input A; inout [7:0] B; output [7:0] C; // declarations // description of f endmodule ModF f f A B C

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 8 ) Module instantiation module ModG (AA, BB, CC); input AA; inout [7:0] BB; output [7:0] CC; wire a; wire [7:0] b; // description of g ModF Umodf (.A(a),.B(b),.C(CC)); endmodule ModG g g AA BB CC f f a b ModF f f A B C instantiation Port connection Instance name Module name

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 9 ) Port Ports provide a means of interconnecting a hardware description consisting of modules, primitives, and macromodules. Port-list It follows module identifier after the keyword module. module module_name (port_list); port_list ::= [port [, port […]]] Port declaration input output inout bidirectional input output inout

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 10 ) Port connection Connecting module instance ports by ordered list Positional mapping The ports expressions listed for the module instance shall be in the same order as the ports listed in the module declaration. Connecting module instance ports by name Named mapping module topmod; wire [4:0] v; wire a,b,c,w; modB b1 (v[0], v[3], w, v[4]); endmodule module modB (wa, wb, c, d); inout wa, wb; input c, d; tranif1 g1 (wa, wb, cinvert); not #(2, 6) n1 (cinvert, int); and #(6, 5) g2 (int, c, d); endmodule module topmod; wire [4:0] v; wire a,b,c,w; modB b1 (.wb(v[3]),.wa(v[0]),.d(v[4]),.c(w)); endmodule module modB (wa, wb, c, d); inout wa, wb; input c, d; tranif1 g1(wa, wb, cinvert); not #(6, 2) n1(cinvert, int); and #(5, 6) g2(int, c, d); endmodule

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 11 ) Port connection rules All input ports must be net. All inout ports must be net. Output port can be either net or reg. input output inout reg or net net reg or net

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 12 ) Parameter Parameters are constants, not variables. Parameter represents constant since it cannot be modified at simulation time. Parameter can have default value. Parameter can be assigned by expression. Parameter can be modified in the module instance statement. The order is important. module my_memory(addr, datai, datao, rw, clk); parameter ADD_WIDTH = 1, DATA_WIDTH = 8; parameter DELAY=0; input [ADD_WIDTH-1:0] addr; input [DATA_WIDTH-1:0] datai; output [DATA_WIDTH-1:0] datao; input rw; input clk; // parameter MEM_DEPTH = 1<<ADD_WIDTH; reg [DATA_WIDTH-1:0] mem[0:MEM_DEPTH-1]; (posedge clk) begin if (rw) #(DELAY) datao = mem[addr]; else mem[addr] = datai; end endmodule // module top;... my_memory UmemA (addA, datA, rw, clk); my_memory #(3,4) UmemB (addB, datB, rw, clk); my_memory #(3,4,2) UmemC (addC, datC, rw, clk); my_memory #(,,3) UmemC (addD, datD, rw, clk);... endmodule Parameter overriding Default parameter Equation is possible Comma-separate list is possible.

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 13 ) Parameter: example (1/3) // mem_generic.v `timescale 1ns/1ns module mem_generic(add, datr, datw, en, we, clk, rstb); parameter ADD_WIDTH=8, DAT_WIDTH=8; parameter DELAY=0; // input [ADD_WIDTH-1:0] add; wire [ADD_WIDTH-1:0] add; output [DAT_WIDTH-1:0] datr; reg [DAT_WIDTH-1:0] datr; input [DAT_WIDTH-1:0] datw; wire [DAT_WIDTH-1:0] datw; input en; wire en; input we; wire we; input clk; wire clk; input rstb; wire rstb; // localparam DEPTH = 1<<ADD_WIDTH; // reg [DAT_WIDTH-1:0] mem[0:DEPTH-1]; // (posedge clk or negedge rstb) begin if (rstb==1'b0) begin datr <= {DAT_WIDTH{1'b0}}; end else begin if (en==1'b1) begin if (we==1'b1) begin datr <= #(DELAY) datw; mem[add] <= datw; end else begin datr <= #(DELAY) mem[add]; end endmodule code/verilog/module/parameter example Width specified by parameters Generic memory model, where address width, data width and response time are specified by parameters Assignment delay specified by parameter. Internal local parameter Storage elements DIY

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 14 ) Parameter: example (2/3) // top.v `timescale 1ns/1ns module top; parameter AW=8, DW=8; reg [AW-1:0] add; reg [DW-1:0] datw; wire [DW-1:0] datrA, datrB; wire [3:0] datrC; reg en, we; reg clk, rstb; integer x; // mem_generic UA (add, datrA, datw, en, we, clk, rstb); mem_generic #(8,8,2) UB (add, datrB, datw, en, we, clk, rstb); mem_generic #(5,4,5) UC (add[4:0], datrC[3:0], datw[3:0], en, we, clk, rstb); // (*) #5 clk <= ~clk; initial begin add <= {AW{1'b0}}; datw <= {DW{1'b0}}; en <= 1'b0; we <= 1'b0; clk <= 1'b0; rstb <= 1'b1; #33 rstb <= 1'b0; #50 rstb <= 1'b1; end // details are not shown.. endmodule code/verilog/module/parameter example Different memory models are instantiated using parameter assignmemt. DIY

Copyright © by Ando KiIntroduction to Verilog-HDL module ( 15 ) Parameter: example (3/3) Note the delay and bus width DIY