Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 8 – Memory Basics Logic and Computer Design Fundamentals

Chapter 8 2 Overview Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits Cells and slices Cell arrays and coincident selection Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types Synchronous (SDRAM) Double-Data Rate (DDR SRAM) RAMBUS DRAM (RDRAM) Arrays of DRAM integrated circuits

Chapter 8 3 Memory Definitions Memory A collection of storage cells together with the necessary circuits to transfer information to and from them. Memory Organization the basic architectural structure of a memory in terms of how data is accessed. Random Access Memory (RAM) a memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell selected. Memory Address A vector of bits that identifies a particular memory element (or collection of elements).

Chapter 8 4 Memory Definitions (Continued) Typical data elements are: bit a single binary digit byte a collection of eight bits accessed together word a collection of binary bits whose size is a typical unit of access for the memory. It is typically a power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.) Memory Data a bit or a collection of bits to be stored into or accessed from memory cells. Memory Operations operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).

Chapter 8 5 Memory Organization Organized as an indexed array of words. Value of the index for each word is the memory address. Often organized to fit the needs of a particular computer architecture. Some historically significant computer architectures and their associated memory organization: Digital Equipment Corporation PDP-8 – used a 12-bit address to address bit words. IBM 360 – used a 24-bit address to address 16,777,216 8-bit bytes, or 4,194, bit words. Intel 8080 – (8-bit predecessor to the 8086 and the current Intel processors) used a 16-bit address to address 65,536 8-bit bytes.

Chapter 8 6 Memory Block Diagram A basic memory system is shown here: k address lines are decoded to address 2 k words of memory. Each word is n bits. Read and Write are single control lines defining the simplest of memory operations. n Data Input Lines k Address Lines Read Write n Data Output Lines Memory Unit 2 k Words n Bits per Word k 1 1 n n

Chapter 8 7 Memory Organization Example Example memory contents: A memory with 3 address bits & 8 data bits has: k = 3 and n = 8 so 2 3 = 8 addresses labeled 0 to = 8 words of 8-bit data

Chapter 8 8 Basic Memory Operations Memory operations require the following: Data data written to, or read from, memory as required by the operation. Address specifies the memory location to operate on. The address lines carry this information into the memory. Typically: n bits specify locations of 2 n words. An operation Information sent to the memory and interpreted as control information which specifies the type of operation to be performed. Typical operations are READ and WRITE. Others are READ followed by WRITE and a variety of operations associated with delivering blocks of data. Operation signals may also specify timing info.

Chapter 8 9 Basic Memory Operations (continued) Read Memory an operation that reads a data value stored in memory: Place a valid address on the address lines. Wait for the read data to become stable. Write Memory an operation that writes a data value to memory: Place a valid address on the address lines and valid data on the data lines. Toggle the memory write control line

Chapter 8 10 Memory Operation Timing Most basic memories are asynchronous Storage in latches or storage of electrical charge No clock Controlled by control inputs and address Timing of signal changes and data observation is critical to the operation Read timing: Read cycle Clock Address Memory enable Read/ Write Data output 20 ns T1T2T3T4T1 Address valid 65 ns Data valid

Chapter 8 11 Memory Operation Timing Write timing: Critical times measured with respect to edges of write pulse (1-0-1): Address must be established at least a specified time before 1-0 and held for at least a specified time after 0-1 to avoid disturbing stored contents of other addresses Data must be established at least a specified time before 0-1 and held for at least a specified time after 0-1 to write correctly Write cycle Clock Address Memory enable Read/ Write Data input 20 ns T1T2T3T4T1 Address valid Data valid 75 ns

Chapter 8 12 RAM Integrated Circuits Types of random access memory Static – information stored in latches Dynamic – information stored as electrical charges on capacitors Charge leaks off Periodic refresh of charge required Dependence on Power Supply Volatile – loses stored information when power turned off Non-volatile – retains information when power turned off

Array of storage cells used to implement static RAM Storage Cell SR Latch Select input for control Dual Rail Data Inputs B and B Dual Rail Data Outputs C and C Chapter 8 13 Static RAM Cell Select B RAM cell C C B S R Q Q

Chapter 8 14 Static RAM Bit Slice Represents all circuitry that is required for 2 n 1-bit words Multiple RAM cells Control Lines: Word select i – one for each word Bit Select Data Lines: Data in Data out

Chapter 8 15 Read/ 2 n -Word 1-Bit RAM IC To build a RAM IC from a RAM slice, we need: Decoder decodes the n address lines to 2 n word select lines A 3-state buffer on the data output permits RAM ICs to be combined into a RAM with c 2 n words Word select Read/Write logic Data in Data out Write Bit select (b) Block diagram RAM cell RAM cell RAM cell Data input Chip select Read/Write Data output A 3 A 2 A 1 A to-16 Decoder A 3 A 2 A 1 A 0 Data input Data output (a) Symbol Read/ Write Memory enable 16 x 1 RAM

Chapter 8 16 Memory arrays can be very large => Large decoders Large fanouts for the bit lines The decoder size and fanouts can be reduced by approximately by using a coincident selection in a 2-dimensional array Uses two decoders, one for words and one for bits Word select becomes Row select Bit select becomes Column select See next slide for example A 3 and A 2 used for Row select A 1 and A 0 for Column select Cell Arrays and Coincident Selection

Chapter 8 17 Cell Arrays and Coincident Selection (continued) Data input Read/Write XXX A 1 A 0 RAM cell Read/Write logic Data in Data out Read/ Write Bit select RAM cell Read/Write logic Data in Data out Read/ Write Bit select RAM cell RAM cell 14 Read/Write logic Data in Data out Read/ Write Bit select RAM cell RAM cell 15 Read/Write logic Data in Data out Read/ Write Bit select Column decoder 2-to-4 Decoder with enable Column select 2 Enable 3 Chip select Data output Row select Row decoder A 2 A 3 X 2-to-4 Decoder

Chapter 8 18 RAM ICs with > 1 Bit/Word Word length can be quite high. To better balance the number of words and word length, use ICs with > 1 bit/word See Figure 8-8 for example 2 Data input bits 2 Data output bits Row select selects 4 rows Column select selects 2 pairs of columns

Chapter 8 19 Making Larger Memories Using the CS lines, we can make larger memories from smaller ones by tying all address, data, and R/W lines in parallel, and using the decoded higher order address bits to control CS. Using the 4-Word by 1- Bit memory from before, we construct a 16-Word by 1-Bit memory.

Chapter 8 20 Making Wider Memories To construct wider memories from narrow ones, we tie the address and control lines in parallel and keep the data lines separate. For example, to make a 4- word by 4-bit memory from 4, 4-word by 1-bit memories Note: Both 16x1 and 4x4 memories take 4-chips and hold 16 bits of data.

Chapter 8 21 Dynamic RAM (DRAM) Basic Principle: Storage of information on capacitors. Charge and discharge of capacitor to change stored value Use of transistor as switch to: Store charge Charge or discharge See next slide for circuit, hydraulic analogy, and logical model.

Chapter 8 22 Dynamic RAM (continued) (a) (c) Select D C Q B DRAM cell model C (f)(g)(h) Select B T C DRAM cell To Pump (b) (d) (e) Stored 1 Stored 0 Write 1 Write 0 Read 1 Read 0

Chapter 8 23 Dynamic RAM - Bit Slice C is driven by 3-state drivers Sense amplifier is used to change the small voltage change on C into H or L In the electronics, B, C, and the sense amplifier output are connected to make destructive read into non-destructive read

Chapter 8 24 Dynamic RAM - Block Diagram Block Diagram – See Figure 8-14 in text Refresh Controller and Refresh Counter Read and Write Operations Application of row address Application of column address Why is the address split? Why is the row address applied first?

Chapter 8 25 Dynamic RAM Read Timing Read cycle 20 ns T1T2T3T4T1 Data valid 65 ns Hi-Z Read/ Write Data output Clock Row Address Column Address RAS CAS Address Output enable

Chapter 8 26 DRAM Types Types to be discussed Synchronous DRAM (SDRAM) Double Data Rate SDRAM (DDR SDRAM) RAMBUS ® DRAM (RDRAM) Justification for effectiveness of these types DRAM often used as a part of a memory hierarchy (See details in chapter 14) Reads from DRAM bring data into lower levels of the hierarchy Transfers from DRAM involve multiple consecutively addressed words Many words are internally read within the DRAM ICs using a single row address and captured within the memory This read involves a fairly long delay

Chapter 8 27 DRAM Types (continued) Justification for effectiveness of these types (continued) These words are then transferred out over the memory data bus using a series of clocked transfers These transfers have a low delay, so several can be done in a short time The column address is captured and used by a synchronous counter within the DRAM to provide consecutive column addresses for the transfers burst read – the resulting multiple word read from consecutive addresses

Chapter 8 28 Synchronous DRAM Transfers to and from the DRAM are synchronize with a clock Synchronous registers appear on: Address input Data input Data output Column address counter for addressing internal data to be transferred on each clock cycle beginning with the column address counts up to column address + burst size – 1 Example: Memory data path width: 1 word = 4 bytes Burst size: 8 words = 32 bytes Memory clock frequency: 5 ns Latency time (from application of row address until first word available): 4 clock cycles Read cycle time: (4 + 8) x 5 ns = 60 ns Memory Bandwidth: 32/(60 x ) = 533 Mbytes/sec

Chapter 8 29 Double Data Rate Synchronous DRAM Transfers data on both edges of the clock Provides a transfer rate of 2 data words per clock cycle Example: Same as for synchronous DRAM Read cycle time = 60 ns Memory Bandwidth: (2 x 32)/(60 x ) = Mbytes/sec

Chapter 8 30 RAMBUS DRAM (RDRAM) Uses a packet-based bus for interaction between the RDRAM ICs and the memory bus to the processor The bus consists of: A 3-bit row address bus A 5-bit column address bus A 16 or 18-bit (for error correction) data bus The bus is synchronous and transfers on both edges of the clock Packets are 4-clock cycles long giving 8 transfers per packet representing: A 12-bit row address packet A 20-bit column address packet A 128 or 144-bit data packet Multiple memory banks are used to permit concurrent memory accesses with different row addresses The electronic design is sophisticated permitting very fast clock speeds

Chapter 8 31 Arrays of DRAM Integrated Circuits Similar to arrays of SRAM ICs, but there are differences typically handled by an IC called a DRAM controller: Separation of the address into row address and column address and timing their application Providing RAS and CAS and timing their application Performing refresh operations at required intervals Providing status signals to the rest of the system (e.g., indicating whether or not the memory is active or is busy performing refresh)

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